core.cpuid

Identify the characteristics of the host CPU, providing information about cache sizes and assembly optimisation hints. This module is provided primarily for assembly language programmers.

References: Some of this information was extremely difficult to track down. Some of the documents below were found only in cached versions stored by search engines! This code relies on information found in:

  • "Intel(R) 64 and IA-32 Architectures Software Developers Manual,

    Volume 2A: Instruction Set Reference, A-M" (2007).

  • "AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).

  • "AMD Processor Recognition Application Note For Processors Prior to AMD

    Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).

  • "AMD Geode(TM) GX Processors Data Book",

    Advanced Micro Devices, Publication ID 31505E, (2005).

  • "AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).

  • "Application note 106: Software Customization for the 6x86 Family",

    Cyrix Corporation, Rev 1.5 (1998)

  • http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf
  • "Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution",

    National Semiconductor, (2002)

  • "The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).

  • http://www.sandpile.org/ia32/cpuid.htm
  • http://www.akkadia.org/drepper/cpumemory.pdf
  • "What every programmer should know about memory",

    Ulrich Depper, Red Hat, Inc., (2007).

  • "CPU Identification by the Windows Kernel", G. Chappell (2009).

    http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm

  • "Intel(R) Processor Identification and the CPUID Instruction, Application

    Note 485" (2009).

Bugs

Currently only works on x86 and Itanium CPUs.

Many processors have bugs in their microcode for the CPUID instruction, so sometimes the cache information may be incorrect.

Types 1

structCacheInfo

Cache size and behaviour

Fields
size_t sizeSize of the cache, in kilobytes, per CPU. For L1 unified (data + code) caches, this size is half the physical size. (we don't halve it for larger sizes, since normally data size is much greater tha...
ubyte associativityNumber of ways of associativity, eg: 1 = direct mapped 2 = 2-way set associative 3 = 3-way set associative ubyte.max = fully associative
uint lineSizeNumber of bytes read into the cache when a cache miss occurs.

Functions 48

fnconst(CacheInfo)[5] dataCaches() @property pure @trusted nothrow @nogcThe data caches. If there are fewer than 5 physical caches levels, the remaining levels are set to size_t.max (== entire memory space)
fnstring vendor() @property pure @trusted nothrow @nogcReturns vendor string, for display purposes only. Do NOT use this to determine features! Note that some CPUs have programmable vendorIDs.
fnstring processor() @property pure @trusted nothrow @nogcReturns processor string, for display purposes only
fnbool x87onChip() @property pure @trusted nothrow @nogcDoes it have an x87 FPU on-chip?
fnbool mmx() @property pure @trusted nothrow @nogcIs MMX supported?
fnbool sse() @property pure @trusted nothrow @nogcIs SSE supported?
fnbool sse2() @property pure @trusted nothrow @nogcIs SSE2 supported?
fnbool sse3() @property pure @trusted nothrow @nogcIs SSE3 supported?
fnbool ssse3() @property pure @trusted nothrow @nogcIs SSSE3 supported?
fnbool sse41() @property pure @trusted nothrow @nogcIs SSE4.1 supported?
fnbool sse42() @property pure @trusted nothrow @nogcIs SSE4.2 supported?
fnbool sse4a() @property pure @trusted nothrow @nogcIs SSE4a supported?
fnbool aes() @property pure @trusted nothrow @nogcIs AES supported
fnbool hasPclmulqdq() @property pure @trusted nothrow @nogcIs pclmulqdq supported
fnbool hasRdrand() @property pure @trusted nothrow @nogcIs rdrand supported
fnbool avx() @property pure @trusted nothrow @nogcIs AVX supported
fnbool vaes() @property pure @trusted nothrow @nogcIs VEX-Encoded AES supported
fnbool hasVpclmulqdq(){return @property pure @trusted nothrow @nogcIs vpclmulqdq supported
fnbool fma() @property pure @trusted nothrow @nogcIs FMA supported
fnbool fp16c() @property pure @trusted nothrow @nogcIs FP16C supported
fnbool avx2() @property pure @trusted nothrow @nogcIs AVX2 supported
fnbool hle() @property pure @trusted nothrow @nogcIs HLE (hardware lock elision) supported
fnbool rtm() @property pure @trusted nothrow @nogcIs RTM (restricted transactional memory) supported
fnbool avx512f() @property pure @trusted nothrow @nogcIs AVX512F supported
fnbool hasRdseed() @property pure @trusted nothrow @nogcIs rdseed supported
fnbool hasSha() @property pure @trusted nothrow @nogcIs SHA supported
fnbool amd3dnow() @property pure @trusted nothrow @nogcIs AMD 3DNOW supported?
fnbool amd3dnowExt() @property pure @trusted nothrow @nogcIs AMD 3DNOW Ext supported?
fnbool amdMmx() @property pure @trusted nothrow @nogcAre AMD extensions to MMX supported?
fnbool hasFxsr() @property pure @trusted nothrow @nogcIs fxsave/fxrstor supported?
fnbool hasCmov() @property pure @trusted nothrow @nogcIs cmov supported?
fnbool hasRdtsc() @property pure @trusted nothrow @nogcIs rdtsc supported?
fnbool hasCmpxchg8b() @property pure @trusted nothrow @nogcIs cmpxchg8b supported?
fnbool hasCmpxchg16b() @property pure @trusted nothrow @nogcIs cmpxchg8b supported?
fnbool hasSysEnterSysExit() @property pure @trusted nothrow @nogcIs SYSENTER/SYSEXIT supported?
fnbool has3dnowPrefetch() @property pure @trusted nothrow @nogcIs 3DNow prefetch supported?
fnbool hasLahfSahf() @property pure @trusted nothrow @nogcAre LAHF and SAHF supported in 64-bit mode?
fnbool hasPopcnt() @property pure @trusted nothrow @nogcIs POPCNT supported?
fnbool hasLzcnt() @property pure @trusted nothrow @nogcIs LZCNT supported?
fnbool isX86_64() @property pure @trusted nothrow @nogcIs this an Intel64 or AMD 64?
fnbool isItanium() @property pure @trusted nothrow @nogcIs this an IA64 (Itanium) processor?
fnbool hyperThreading() @property pure @trusted nothrow @nogcIs hyperthreading supported?
fnuint threadsPerCPU() @property pure @trusted nothrow @nogcReturns number of threads per CPU
fnuint coresPerCPU() @property pure @trusted nothrow @nogcReturns number of cores in CPU
fnbool preferAthlon() @property pure @trusted nothrow @nogcOptimisation hints for assembly code.
fnbool preferPentium4() @property pure @trusted nothrow @nogcDoes this CPU perform better on Pentium4 code than PentiumPro..Core2 code?
fnbool preferPentium1() @property pure @trusted nothrow @nogcDoes this CPU perform better on Pentium I code than Pentium Pro code?
fnuint cacheLevels() @property @trusted nothrow @nogcThe number of cache levels in the CPU.

Variables 3

varCacheInfo[5] datacache

Scheduled for deprecation. Please use dataCaches instead.

varuint stepping

Warning: This field will be turned into a property in a future release.

Processor type (vendor-dependent). This should be visible ONLY for display purposes.

varuint numCacheLevels = 1

This field has been deprecated. Please use cacheLevels instead.